" " BEGIN INCLUDE FILE mc.incl.alm 6/72 SHW " Modified 8/80 by J. A. Bush for dps8/70M CPU " " General layout of data items. equ mc.prs,0 pointer registers equ mc.regs,16 registers equ mc.scu,24 SCU data equ mc.eis_info,40 pointers and lengths for EIS " Temporary storage for software equ mc.mask,32 system controller mask at time of fault equ mc.ips_temp,34 temporary storage for IPS info equ mc.errcode,35 error code equ mc.fim_temp,36 temporary to hold fault index and unique index equ mc.fault_reg,37 fault register equ mc.fault_time,38 time of fault equ mc.cpu_type_word,38 CPU type from rsw (2). overlays part of time word bool mc.cpu_type_mask,300000 DU equ mc.ext_fault_reg,38 ext fault reg for dps8. overlays part of time word bool mc.ext_fault_reg_mask,77774 DU equ mc.cpu_type_shift,3 positions to shift right or left " SCU DATA " WORD (0) PROCEDURE POINTER REGISTER equ mc.scu.ppr.prr_word,24 Procedure Ring Register equ scu.ppr.prr_word,0 bool scu.ppr.prr_mask,700000 DU equ scu.ppr.prr_shift,33 equ mc.scu.ppr.psr_word,24 Procedure Segment Register equ scu.ppr.psr_word,0 bool scu.ppr.psr_mask,077777 DU equ scu.ppr.psr_shift,18 equ mc.scu.ppr.p_word,24 Procedure Privileged Bit equ scu.ppr.p_word,0 bool scu.ppr.p,400000 DL " APPENDING UNIT STATUS equ mc.scu.apu_stat_word,24 APPENDING UNIT STATUS equ scu.apu_stat_word,0 bool scu.apu.xsf,200000 DL - Ext Seg Flag - IT mod. bool scu.apu.sdwm,100000 DL - Match in SDW Ass. Mem. bool scu.apu.sd_on,040000 DL - SDW Ass. Mem. ON bool scu.apu.ptwm,020000 DL - Match in PTW Ass. Mem. bool scu.apu.pt_on,010000 DL - PTW Ass. Mem. ON bool scu.apu.pi_ap,004000 DL - Instr fetch or Append cycle bool scu.apu.dsptw,002000 DL - Fetch of DSPTW bool scu.apu.sdwnp,001000 DL - Fetch of SDW non-paged bool scu.apu.sdwp,000400 DL - Fetch of SDW paged bool scu.apu.ptw,000200 DL - Fetch of PTW bool scu.apu.ptw2,000100 DL - Fetch of pre-paged PTW bool scu.apu.fap,000040 DL - Fetch of final address paged bool scu.apu.fanp,000020 DL - Fetch final address non-paged bool scu.apu.fabs,000010 DL - Fetch of final address absolute equ mc.scu.fault_cntr_word,24 Num of retrys of EIS instructions. equ scu.fault_cntr_word,0 bool scu.fault_cntr_mask,000007 " WORD (1) FAULT DATA equ mc.scu.fault_data_word,25 FAULT DATA equ scu.fault_data_word,1 bool scu.fd.iro,400000 DU - Illegal Ring Order bool scu.fd.oeb,200000 DU - Not In Execute Bracket bool scu.fd.e_off,100000 DU - No Execute bool scu.fd.orb,040000 DU - Not In Read Bracket bool scu.fd.r_off,020000 DU - No Read bool scu.fd.owb,010000 DU - Not In Write Bracket bool scu.fd.w_off,004000 DU - No Write bool scu.fd.no_ga,002000 DU - Not A Gate bool scu.fd.ocb,001000 DU - Not in Call Bracket bool scu.fd.ocall,000400 DU - Outward Call bool scu.fd.boc,000200 DU - Bad Outward Call bool scu.fd.inret,000100 DU - Inward Return bool scu.fd.crt,000040 DU - Cross Ring Transfer bool scu.fd.ralr,000020 DU - Ring Alarm bool scu.fd.am_er,000010 DU - Assoc. Mem. Fault bool scu.fd.oosb,000004 DU - Out Of Bounds bool scu.fd.paru,000002 DU - Parity Upper bool scu.fd.parl,000001 DU - Parity Lower bool scu.fd.onc_1,400000 DL - Op Not Complete bool scu.fd.onc_2,200000 DL - Op Not Complete " GROUP II FAULT DATA bool scu.fd.isn,400000 DU - Illegal Segment Number bool scu.fd.ioc,200000 DU - Illegal Op Code bool scu.fd.ia_im,100000 DU - Illegal Addr - Modifier bool scu.fd.isp,040000 DU - Illegal Slave Procedure bool scu.fd.ipr,020000 DU - Illegal Procedure bool scu.fd.nea,010000 DU - Non Existent Address bool scu.fd.oobb,004000 DU - Out Of Bounds equ mc.scu.port_stat_word,25 PORT STATUS equ scu.port_stat_word,1 bool scu.ial_mask,170000 DL - Illegal Action Lines equ scu.ial_shift,12 bool scu.iac_mask,007000 DL - Illegal Action Channel equ scu.iac_shift,9 bool scu.con_chan_mask,000700 DL - Connect Channel equ scu.con_chan_shift,6 bool scu.fi_num_mask,000076 DL - Fault / Interrupt Number equ scu.fi_num_shift,1 bool scu.fi_flag_mask,000001 DL - Fault / Interrupt Flag " WORD (2) TEMPORARY POINTER REGISTER equ mc.scu.tpr.trr_word,26 Temporary Ring Register equ scu.tpr.trr_word,2 bool scu.tpr.trr_mask,700000 DU equ scu.tpr.trr_shift,33 equ mc.scu.tpr.tsr_word,26 Temporary Segment Register equ scu.tpr.tsr_word,2 bool scu.tpr.tsr_mask,077777 DU equ scu.tpr.tsr_shift,18 equ mc.scu.cpu_no_word,26 CPU Number equ scu.cpu_no_word,2 bool scu.cpu_no_mask,000700 DL equ scu.cpu_shift,6 equ mc.scu.delta_word,26 Tally Modification DELTA equ scu.delta_word,2 bool scu.delta_mask,000077 DL " WORD (3) TSR STATUS equ mc.scu.tsr_stat_word,27 TSR STATUS for 1,2, and 3 equ scu.tsr_stat_word,3 Word Instructions bool scu.tsr_stat_mask,777700 DL - All of Status equ scu.tsr_stat_shift,6 bool scu.tsna_mask,740000 DL - Word 1 Status bool scu.tsna.prn_mask,700000 DL - Word 1 PR num equ scu.tsna.prn_shift,15 bool scu.tsna.prv,040000 DL - Word 1 PR valid bit bool scu.tsnb_mask,036000 DL - Word 2 Status bool scu.tsnb.prn_mask,034000 DL - Word 2 PR num equ scu.tsnb.prn_shift,11 bool scu.tsnb.prv,002000 DL - Word 2 PR valid bit bool scu.tsnc_mask,0013 DL - Word 3 Status bool scu.tsnc.prn_mask,001600 DL - Word 3 PR num equ scu.tsnc.prn_shift,7 bool scu.tsnc.prv,000100 DL - Word 3 PR valid bit equ mc.scu.tpr.tbr_word,27 TPR.TBR Field equ scu.tpr.tbr_word,3 bool scu.tpr.tbr_mask,000077 DL " WORD (4) INSTRUCTION COUNTER equ mc.scu.ilc_word,28 INSTRUCTION COUNTER equ scu.ilc_word,4 equ scu.ilc_shift,18 equ mc.scu.indicators_word,28 INDICATOR REGISTERS equ scu.indicators_word,4 bool scu.ir.zero,400000 DL - Zero Indicator bool scu.ir.neg,200000 DL - Negative Indicator bool scu.ir.carry,100000 DL - Carry Indicator bool scu.ir.ovfl,040000 DL - Overflow Indicator bool scu.ir.eovf,020000 DL - Exponent Overflow Ind bool scu.ir.eufl,010000 DL - Exponent Underflow Ind bool scu.ir.oflm,004000 DL - Overflow Mask Indicator bool scu.ir.tro,002000 DL - Tally Runout Indicator bool scu.ir.par,001000 DL - Parity Indicator bool scu.ir.parm,000400 DL - Parity Mask Indicator bool scu.ir.bm,000200 DL - Bar Mode Indicator bool scu.ir.tru,000100 DL - Truncation Indicator bool scu.ir.mif,000040 DL - Multiword Indicator bool scu.ir.abs,000020 DL - Absolute Indicator bool scu.ir.hex,000010 DL - Hexadecimal Indicator " WORD (5) COMPUTED ADDRESS equ mc.scu.ca_word,29 COMPUTED ADDRESS equ scu.ca_word,5 equ scu.ca_shift,18 equ mc.scu.cu_stat_word,29 CONTROL UNIT STATUS equ scu.cu_stat_word,5 bool scu.cu.rf,400000 DL - Repeat First " On First Cycle of Repeat Inst. bool scu.cu.rpt,200000 DL - Repeat Instruction bool scu.cu.rd,100000 DL - Repeat Double Instr. bool scu.cu.rl,040000 DL - Repeat Link Instr. bool scu.cu.pot,020000 DL - IT Modification bool scu.cu.pon,010000 DL - Return Type Instruction bool scu.cu.xde,004000 DL - XDE from Even Location bool scu.cu.xdo,002000 DL - XDE from Odd Location bool scu.cu.poa,001000 DL - Operand Preparation bool scu.cu.rfi,000400 DL - Tells CPU to refetch instruction " This Bit Not Used (000200) bool scu.cu.if,000100 DL - Fault occurred during instruction fetch equ mc.scu.cpu_tag_word,29 Computed Tag Field equ scu.cpu_tag_word,5 bool scu.cpu_tag_mask,000007 DL " WORDS (6,7) INSTRUCTIONS equ scu.even_inst_word,30 Even Instruction equ scu.odd_inst_word,31 Odd Instruction " END INCLUDE FILE incl.alm " " " ----------------------------------------------------------- " " " " Historical Background " " This edition of the Multics software materials and documentation is provided and donated " to Massachusetts Institute of Technology by Group Bull including Bull HN Information Systems Inc. " as a contribution to computer science knowledge. " This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology, " Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell Bull Inc., Groupe Bull " and Bull HN Information Systems Inc. to the development of this operating system. " Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970), " renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership " of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture for " managing computer hardware properly and for executing programs. Many subsequent operating systems " incorporated Multics principles. " Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc., " as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. . " " ----------------------------------------------------------- " " Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without " fee is hereby granted,provided that the below copyright notice and historical background appear in all copies " and that both the copyright notice and historical background and this permission notice appear in supporting " documentation, and that the names of MIT, HIS, Bull or Bull HN not be used in advertising or publicity pertaining " to distribution of the programs without specific prior written permission. " Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc. " Copyright 2006 by Bull HN Information Systems Inc. " Copyright 2006 by Bull SAS " All Rights Reserved " "